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The OR bit is used for combining AND functions before OR functions. The fourth is the Assign instruction which takes the RLO and writes it out to the corresponding address. In this case the final RLO = 0 so the output will be off. If M0.0 was 1 then the “And” operation will evaluate to true making the RLO = 1 which will then turn on the output Q1.0.The same thing happens on the second line but this time 1 and 0 makes the current RLO = 0.On the second line, the /FC bit is now 1 indicating that this line needs to use the RLO from the previous line. The address I1.1 is on so the STA = 1. The RLO from the last line is 1 and this is ‘anded’ with the current STA with a result of 1 in the current RLO.At the start the First Check bit (/FC) is zero so an And instruction will logically mirror the Status bit (STA) over to the Result of Logic Operation (RLO). In this case the address I0.0 is 1 so the STA is one and the result of the logic (RLO) will be 1. The A instruction writes a 1 to /FC.

If you are used to ladder logic and struggling to understand the purpose of the RLO and STA it may help to visualize a rung like below. The STA is used to keep track of the state of the addresses. The RLO is used to keep track of the state of the rung.

The STA bit reflects the state of the current Boolean address. The RLO bit stores the running logic state of the currently processing instructions. Certain bit logic and comparison instruction will turn the RLO to a 1 when the condition is TRUE and write a 0 when the condition is FALSE. Other instructions read the RLO (=, S, R) to determine how they are to execute. RLO – Result of Logic Operation (bit 1) If the /FC bit is a 0 then the instruction is considered to be the first instruction being processed. If the /FC is a 1 then the instruction being scanned will use the logic from the previous instruction. Certain instructions like =, S and R will set the /FC bit to 0 thus starting new logic after it. Other instructions like A or O will set the /FC bit to 1 signalling to combine the logic with the next instruction. The status word can be seen by displaying the STATUS column while monitoring in STL view. The RLO (bit 1) and the STA (bit 2) are also displayed in the RLO and STA column. In Siemens PLCs the Status Word is an internal CPU register used to keep track of the state of the instructions as they are being processed. In order to use STL more effectively it is important to understand the Status Word and its functions.Įach bit in the Status Word has a specific function to keep track of bit logic (RLO, STA), math (OV, OS), comparison operations (CC0, CC1) and whether the logic should continue, be nested or start new (/FC, OR, BR). Only the first 9 of the 16 bits are used.Įach instruction may do the following to each bit in the status word.